001 : Emotion Classification Algorithm and Its Implementation on FPGA via VHDL

In this project, I utilized Deep Learning with a VHDL project. The training of the emotion classifier took 5 months prior to the project proposal. Different from what is available on the web, I have improved the accuracy of the model from 65% to 80%. There is a bias towards the 'sad' emotion class, however, I compensate it with minor calibrations. Since this is a VHDL project the main logic is located in the FPGA. The computer and python are only used for face and emotion detection. The data processing occurs at Basys3. When the emotion data arrives over the UART, the VHDL design recognizes the data and drives the servos and seven-segment display accordingly. Furthermore, for testing purposes, users may give custom inputs rather than UART. Further information can be found at Github, Youtube and Google Colab.

Emotion: Angry

Emotion: Suprised